View TMC2067P7C_5972496.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary information preliminary information describes products that are not in full production at the time of printing. specifications are based on design goals and limited characterization. they may change without notice. contact fairchild semiconductor for current information. www.fairchildsemi.com features analog composite and yc input processing 10-bit digital composite and yc outputs fairchild demo board compatibility applications evaluation of tmc1185, 10-bit a/d evaluation of tmc2242, decimation ?ter input to the tmc2068p7c decoder demonstration board. description the TMC2067P7C provides a high quality 10-bit front end for the tmc22153 digital decoder. composite and yc inputs are clamped and ?tered before being oversampled in the tmc1185 10-bit a/d. the a/d outputs are decimated in tmc2242 half band ?ters to provide the pixel data to the tmc22153 digital decoder demonstration board. block diagram output to genlock y/comp input s-vhs chroma input digital outputs: 10 bit composite/luma 10 bit chroma 96 way edge connector (male) digital inputs: adc clock clamp signal y/composite lpf and clamp circuit chrominance bpf and clamp circuit sw1 analog front end for the tmc22153 digital decoder tmc1185 tmc1185 sw2 tmc2242 tmc2242 10 bit adcs digital lpfs 65-2067-01 TMC2067P7C dual a/d demonstration board for the tmc1185 10-bit analog-to-digital converter rev. 0.9.0
TMC2067P7C product specification 2 preliminary information functional description the y/comp (luminance/composite) analog input is buffered to a bnc for connection to the tmc22071a genlocking video digitizer on the tmc2068p7c decoder demonstration board. the y/comp signal is also passed through a simple antialiasing low pass ?ter. the ?tered y/comp signal is clamped to the back porch level using the elantec el4390. the clamp pulse is provided by an fpga on the tmc2068p7c decoder demonstration board, which is locked to the horizontal sync produced by the tmc22071a. the clamped y/comp signal is transformed into the differ- ential input signal required by the tmc1185, 10-bit adc. the differential y/comp signal is oversampled in the tmc1185, using the pxck clock from the tmc22071a, and then decimated in the tmc2242 digital low pass ?ter. the chroma (chrominance) analog input is passed through a simple bandsplit ?ter which acts as both the antialiasing ?ter for the tmc1185 and suppresses low frequency noise or signals on the chroma signal. the ?ter output is clamped to the chroma black level using the elantec el4390 using the same clamp pulse used to clamp the y/comp signal. the clamped chroma signal is transformed into the differential input signal required by the tmc1185. the differential chroma signal is oversampled in the tmc1185, using the pxck clock from the tmc22071a, and then decimated in the tmc2242 digital low pass ?ter. the mode of operation of the tmc2242 digital half band ?ters can be independently controlled using the the two dip switches, sw1 and sw2, provided. an s-vhs connector is also provided and is directly coupled to the bncs, therefore care should be taken not to connect inputs to both the bncs and the s-vhs connector simulta- neously. 12-bit option the footprint for the burr brown 12-bit a/d (ads800) is compatible with the fairchild tmc1185 10-bit a/d, it is therefore possible to replace the tmc1185 and recon?ure the tmc2242, using the dip switches, to evaluate the tmc22153 performance with a 12-bit oversampled a/d front end, which is then decimated and rounded to 10-bits. this improves the overall s/n performance by decreasing the noise introduced by the quantization of the video signal. this option is not presently provided, and requires the board to be purchased and modi?d by the customer. however, applications support will be provided to assist in any modi?ations that are required. detailed circuit description composite/luma channel the y or composite input from bnc j1 is terminated at r4 and buffered by u1:a to provide a synchronizing output at j2. in addition a second signal is buffered through u1:b to the edge connector p2b pin 6. optional ac coupling is provided by c3, c4 and r9. u9:b provides the necessary gain to drive the a-d converter and is provided with a gain adjustment, rv3. the output of u9:b drives the anti-alias ?ter consisting of r45, c52, l5, c53, l6, c54 and r47. this ?ter provides a butterworth response with about 30db of attenuation at 13.5mhz. since the ?ter introduces some group delay it is followed by an all-pass delay correction circuit consisting of u9:a and its associated components. (additional correction is provided by the d-a driver/inverter circuit described below.) the output of the anti-alias ?ter at u9:a pin 1 connects to one input of the clamp circuit consisting of u3 and its associated components. c18 provides dc isolation and storage of the clamp potential. the clamp pulse at pin 6 of u3 samples the reference potential at pin 14 to establish the clamp point for the a channel. the optimum position for the clamp pulse is immediately after the color burst to avoid phase and amplitude modulation of the burst. the clamp ampli?r has a gain of two to compensate for the 6db loss through the anti-alias ?ter (set by r24 and r25). the a-d has an input range of 1.25 to 3.25 volts and so the clamp reference voltage is chosen to put the composite signal within this range after a gain of two has been applied. the second channel of the clamp circuit is used as a buffer for the a-d midpoint (cm) reference signal used by the inverters. this is achieved by connecting the clamp reference input of this channel to the ampli?r input and running the ampli?r at unity gain. the clamped a channel signal connects to buffer u10:b and inverter u10:a. both the buffer and inverter are con?ured for all-pass operation in order to provide additional group delay correction. the buffer is mainly required to provide delay matching between the normal and inverted inputs of the a-d converter. the inverter, u10:a obtains its invert reference from the buffered cm output of the a-d ensuring that the a channel signal is inverted about the midpoint of the a-d input range. the normal and inverted outputs from u:10 connect to the differential inputs of the a-d converter, u11, via the ?ter networks consisting of r56, c62 and r52, c57. for a detailed description of the a-d converter operation refer to the fairchild tmc1185 data sheet. the digital output of the a-d converter connects to the tmc2242b decimator, u7, where the pixel rate is halved. for more information on the decimator, refer to the fairchild tmc2242b data sheet. chroma channel the b channel is similar to the a channel except that the anti-alias ?ter is implemented as a bandpass ?ter and the clamp axis is chosen for a bipolar signal (i.e. a-d midpoint reference). the input stage u2:b is ac coupled from j4 via c5 and r11. the svhs connector, j3, bridges the
product specification TMC2067P7C 3 preliminary information y/composite and chroma inputs so that only one set of inputs can be used at a time. the all-pass sections in his channel are primarily used to match the delay through the two channels. engineering notes the following notes relate to the orcad schematics and are supplemental to the circuit description. 1. the clamp circuit is a simple implementation using an elantec el4390 circuit. this circuit provides reasonably good clamping but loads the input during the sample pulse. this can cause a slight phase error if the clamp pulse occurs during the burst period. this can be corrected using the system phase adjustment or eliminated by clamping after the burst. clamping after the burst requires a shorter clamp pulse (about 1-1.5 us). alternately the signal can be sync-tip clamped. 2. the a-d midpoint reference (cm) for the inverters comes from the a channel a-d. this is done to make use of the available buffer in the el4390 and avoid having an additional reference buffer. although there may be a slight difference between the two references the dc level of the chroma channel is not critical since it is re-established in the tmc22x5y. 3. the schematic has been designed for +/- 12v operation. if it is desired to run the system from +/- 5v supplies, it will be necessary to make the following changes: a. replace the el2260 op. amps with el2270 op. amps. b. connect two series connected diodes (1n914 or similar) in series with the outputs of the el4390 at pins 10 and 15 with the cathodes of the diodes towards the output pins of the el4390. add a pull up resistor (470 ohms) from the anode of the last diode and the junction of r9 to +5v. add a similar resistor on the other channel at the junction with r22. c. adjust the clamp reference voltage by changing r13 to 5.6k. since the positive analog and digital supplies may now be the same, care should be taken to provide adequate ?tering for the analog section of the circuit. 4. the power input ?tering from the 96 pin connector uses ferrite beads. this should be adequate provided that the supplies do not have excessive low frequency noise. if the +5v digital supply from the main board is question- able it would be better to run a separate trace direct from the power supply to the 96 pin connector. even using +/- 12v supplies it is still necessary that the +5v supply be reasonably clean since it is driving the a-d converters. 5. it is assumed that the trace length associated with the decimator outputs is relatively short (<4 inches). if this is not the case it may be desirable to add series resistors in the data lines to correctly terminate the lines and avoid inducing ground currents in the submodule. 6. when laying out the pc board, care should be taken to avoid placing the ?ter inductors close together. the optimum placement for horizontally wound inductors is in a t con?uration or with a reasonable separation between them. it is preferable to isolate the +5v ground plane in the analog area although this may not be neces- sary using surface mount components provided the ground plane is situated immediately under the compo- nent layer. we recommend returning the analog and dig- ital grounds separately to the power entry point. this may be achieved with a suitable moat on the ground plane. although in some cases it is desirable to isolate the digital and analog grounds with a bead we do not consider it necessary in this situation. as usual, connec- tions to the inverting inputs of the op amps should be as short as possible as should connections between the pos- itive input and any input resistor.
TMC2067P7C product specification 4 preliminary information dip switch con?urations note: 1. default value. slider switch and jumper con?urations dip switch function when open function when closed swa * correct position for normal operation not recommended, reserved for future use swb * correct position for normal operation not recommended, reserved for future use swc * correct position for normal operation not recommended, reserved for future use swd * correct position for normal operation not recommended, reserved for future use swe dec pin high on u7 1 dec pin low on u7 swf int pin high on u7 1 int pin low on u7 swg * two? complement output on u7 unsigned output on u7 swh * two? complement output on u8 unsigned output on u8 dip switch function when open function when closed swi output disabled on u7 * output enabled on u7 swj output disabled on u8 * output enabled on u8 swk * inverts the msbs of yover[9:0], yadc[9:0], and cadc[9:0]. no inversion of yover[9] swl * inverts the msb of cover[9:0] no inversion of yover[9] swm sets rnd0 high on u7 and u8 sets rnd0 low on u7 and u8 1 swn sets rnd1 high on u7 and u8 1 sets rnd1 low on u7 and u8 swo sets rnd2 high on u7 and u8 1 sets rnd2 low on u7 and u8 swp unused unused board ref. functional description e2 connects the analog composite signal or chrominance signal (*) to the chrominance bpf and gain circuit jp1 terminates the video signal on bnc j2 when connected. e4 & e5 allows a 12-bit signal into u7 when open, truncates to 10-bits when closed(*) e7 & e8 allows a 12-bit signal into u8 when open, truncates to 10-bits when closed(*) e3 disconnects the chroma a/d clock, to reduce board noise if required. e6 disconnects the sync signal from the tmc2242? (*) jp3 terminates the buffered analog video signal on bnc j1 when connected.
product specification TMC2067P7C 5 preliminary information test procedure this test procedure establishes the correct digital data ranges for a ntsc composite video signal. an adjustment to the black level offset will be required for pal composite video signals. 1. set the dip switches as indicated with (*) in the dip switch con?urations section, and the slider switches as directed with (*) in the slider switch con?uration sec- tion. 2. connect a composite video signal to bnc j1. discon- nect any inputs to connectors j3 and j4, or connect a luma signal to bnc j1 and a chroma signal to bnc j4 or a yc input to j3. 3. verify that a ?lean composite signal is on tp2 and tp3. it is essential that a ?lean composite waveform appears on tp2. if tp3 has no signal move the slider on e2. 4. check that a ?lean composite signal appears on tp1, this will be twice the amplitude of the signal on tp2 unless the signal is terminated using jp1. for normal operation this signal should be left unterminated. 5. check that a ?lean composite signal appears on tp22, this will be twice the amplitude of the signal on tp2 unless the signal is terminated using jp3. for normal operation this signal should be left unterminated. 6. check that the ttl clamp pulse on tp9 is locked to the analog video signal on tp2. the clamp pulse should be 0.5 us wide and positioned on the back porch between the burst and the start of active video. 7. to set the composite signal gain, connect a scope probe to tp6. adjust rv3 (clockwise reduces the gain) to establish a peak white (100 ire) signal equal to 576mv. 8. verify that the signal on tp7 is the chrominance signal only, using 75% smpte color bars as the composite input signal. adjust rv1 (clockwise reduces the gain) to establish 340mv on tp7 using the yellow and blue bars as the reference. 9. adjust the black level offset, using rv2, to set 800mv on c15. 10. adjust rv4 to provide a voltage on c21 that is equal to half the average of the voltages on tp8 and u3 pin 5. the following table show the digital data ranges that will be produced if the tmc2076p7c test procedure is followed. figure 1. composite video waveform table 1. 10-bit composite input data ranges color ntsc/m pal/i bar ycyc white 824 0 828 0 yellow 762 +/- 242 763 +/- 257 cyan 663 +/- 341 657 +/- 362 green 601 +/- 319 592 +/- 338 magenta 507 +/- 319 492 +/- 338 red 445 +/- 341 426 +/- 362 blue 345 +/- 242 321 +/- 257 pedestal 284 0 n/a n/a blanking 240 0 256 0 burst 0 +/- 117 0 +/- 122 sync tip 6 0 10 0 65-2067-02
TMC2067P7C product specification 6 preliminary information bill of materials item quantity part number reference 1 1 cr1 red, +5v 2 1 cr2 red, +12v 3 1 cr3 orange, -12v 4 1 cr4 orange, -5v 5 40 c1, c2, c5, c6, c8, c10, c15, c16, c17, c18, c19, c20, c21, c24, c25, c26, c29, c30, c31, c32, c35, c39, c43, c45, c46, c47, c48, c50, c58, c59, c60, c63, c64, c65, c66, c67, c68, c69, c70, c73 0.1 m f 6 2 c4, c3 100 m f/6.3v 7 4 c7, c14, c49, c55 10 m f/25v 8 2 c9, c53 220pf 9 7 c11, c23, c28, c56, c57, c61, c62 22pf 10 2 c13, c12 120pf 11 2 c27, c22 47pf 12 4 c33, c37, c41, c71 22 m f/25v 13 4 c34, c38, c42, c72 0.47 m f/25v 14 4 c36, c40, c44, c74 0.01 m f 15 1 c51 30pf 16 2 c52, c54 68pf 17 8 d1, d2, d3, d4, d5, d6, d7, d8 mmbd301 18 4 d9, d10, d11, d12 1n4004 19 6 e1, e2, e4, e5, e7, e8 select 20 1 e3 adc clk disable 21 1 e6 sync disable 22 4 fb1, fb2, fb3, fb4 f bead 23 5 gnd1, gnd2, gnd3, gnd4, gnd5 gnd 24 2 jp1, jp3 termination 25 1 jp2 power 6 26 3 j1, j2, j4 bnc 27 1 j3 s-video 28 3 l1, l4, l8 10 m h 29 1 l2 4.7 m h 30 1 l3 15 m h 31 3 l5, l6, l7 6.8 m h 32 8 pth1, pth2, pth3, pth4, pth5, pth6, pth7, pth8 pth 33 1 p1 header 96 34 1 p2 euro96m 35 2 rn2, rn1 4.7k 36 2 rv1, rv3 1k pot 37 1 rv2 1k pot 38 1 rv4 500 pot 39 5 r1, r26, r27, r28, r59 75 40 6 r2, r6, r10, r21, r50, r60 220
product specification TMC2067P7C 7 preliminary information 41 3 r3, r4, r12 75 1% 42 22 r5, r7, r8, r14, r15, r20, r34, r36, r37, r38, r40, r41, r43, r44, r49, r51, r53, r54, r55, r57, r58, r61 750 43 4 r9, r11, r62, r63 10k 44 8 r13, r19, r35, r39, r42, r48, r52, r56 47 45 3 r16, r18, r47 200 1% 46 2 r17, r46 1k 47 1 r22 15k 48 1 r23 500 49 5 r24, r25, r31, r32, r33 1.2k 1% 50 2 r30, r29 1k % 51 1 r45 200 52 2 s2, s1 sw dip-8 53 21 tp1, tp2, tp3, tp4, tp5, tp6, tp7, tp8, tp9, tp10, tp11, tp12, tp16, tp17, tp18, tp19, tp20, tp21, tp22, tp23, tp26 tp 54 1 tp13 +5v 55 1 tp14 +12v 56 1 tp15 -12v 57 2 tp25, tp24 coax mount 58 1 tp27 -5v 59 5 u1, u2, u4, u9, u10 el2260c 60 1 u3 el4390c 61 2 u5, u11 tmc1185ndc40 62 1 u6 74f86 63 2 u7, u8 tmc2242br2 bill of materials (continued) item quantity part number reference
TMC2067P7C product specification 8 preliminary information schematics analog_ip analog_ip cm clamp ycomp chroma ref aout adcs adcs.sch ref chroma ycomp clock swk c_clock cm yadc[0..11] cadc[0..11] power power half band filters tmc2242 yadc[0..11] cadc[0..11] sync_ck clock c_clock yover[0..9] cover[0..9] swk edge connector op_conn yover[0..9] cover[0..9] clock clamp sync_ck aout sync_ck clock c_clock clamp cm clock swk cadc[0..11] yadc[0..11] c_clock cm swk clamp cover[0..9] sync_ck clock yover[0..9] aout aout figure 2. adc10b
product specification TMC2067P7C 9 preliminary information schematics (continued) chromaproc chroma acip acop clamp circuit clamp ayop acop cm clamp ycomp ref chroma lumaproc ycomp ayip ayop -12v +12v luma/composite video input chroma video input acip ayip c4 100 f/6.3v + r3 75 1% r8 750 c3 100 f/6.3v + r2 220 r4 75 1% r9 10k j4 bnc 1 2 j2 bnc 1 2 r5 750 j1 bnc 1 2 r12 75 1% r11 10k c5 0.1 f c2 0.1 f c1 0.1 f r7 750 r1 75 e1 select e2 select r10 220 u1a el2260c + - 3 2 1 8 4 u1b el2260c + - 5 6 7 8 4 r6 220 tp1 tp tp2 tp tp3 tp tp4 tp jp1 termination j3 s-video 1 3 4 2 r61 750 r60 220 cm clamp ycomp ref chroma aout figure 3. analog_ip
TMC2067P7C product specification 10 preliminary information schematics (continued) -12v +12v ayip ayop l7 6.8 h c52 68pf l6 6.8 h r45 200 r50 220 c49 10 f/25v + l5 6.8 h c50 0.1 f r49 750 c53 220pf r48 47 l8 10 h c48 0.1 f c54 68pf r47 200 1% r46 1k r43 750 r44 750 c51 30pf u9a el2260c + - 3 2 1 8 4 u9b el2260c + - 5 6 7 8 4 r42 47 rv3 1k pot 1 3 2 c55 10 f/25v + ayip ayop figure 4. ycomp.scii
product specification TMC2067P7C 11 preliminary information schematics (continued) -12v +12v acip acop l2 4.7 h c12 120pf l1 10 h r16 200 1% r21 220 c7 10 f/25v + c10 0.1 f r20 750 l3 15 h r19 47 l4 10 h c6 0.1 f c8 0.1 f c13 120pf r18 200 1% r17 1k r14 750 r15 750 c11 22pf u2a el2260c + - 3 2 1 8 4 u2b el2260c + - 5 6 7 8 4 r13 47 rv1 1k pot 1 3 2 c14 10 f/25v + acip acop c9 220pf figure 5. chroma
TMC2067P7C product specification 12 preliminary information schematics (continued) -12v +12v +12v r26 75 r24 1.2k 1% r25 1.2k 1% r33 1.2k 1% r27 75 r22 15k r23 500 r32 1.2k 1% c18 0.1uf c16 0.1uf c21 0.1uf c20 0.1uf c15 0.1uf r28 75 c19 0.1uf u3 el4390c dgnd 3 vcc 16 vee 9 rin- 1 rin+ 2 gin- 4 gin+ 5 bin- 8 bin+ 7 clamp level r 14 clamp level g 12 clamp level b 11 hold 6 rout 15 gout 13 bout 10 r31 1.2k 1% c17 0.1uf tp6 tp tp7 tp tp9 tp tp5 tp tp8 tp tp10 tp rv2 1k pot 1 3 2 r30 1k % r29 1k % rv4 500 pot 1 3 2 tp26 tp ayop acop cm ref ycomp chroma clamp figure 6. clamp
product specification TMC2067P7C 13 preliminary information schematics (continued) chroma adc c_adc chroma ref clock swk cadc[0..11] c_clock ycomp adc y_adc ycomp ref clock swk yadc[0..11] cm yadc[0..11] ref chroma clock swk cadc[0..11] c_clock yadc[0..11] ycomp swk clock cm cadc[0..11] figure 7. adcs
TMC2067P7C product specification 14 preliminary information schematics (continued) figure 8. yadc.sch -12v +12v vcc vcc vcc vcc decoupling yadc11 yadc10 yadc9 yadc8 yadc7 yadc6 yadc5 yadc4 yadc3 yadc2 yadc[0:11] yadc1 yadc0 r55 750 r58 750 c63 0.1uf c60 0.1uf r57 750 r56 47 c62 22pf c61 22pf r54 750 r52 47 c57 22pf r53 750 r51 750 c56 22pf c66 0.1uf c64 0.1uf c65 0.1uf c58 0.1uf c59 0.1uf u11 tmc1185ndc40 (msb)b1 2 b2 3 b3 4 b4 5 b5 6 b6 7 b7 8 b8 9 b9 10 (lsb)b10 11 clk 16 oe 18 msbi 19 refb 21 cm 22 reft 23 in 26 in 27 dnc 12 dnc 13 u10b el2260c + - 5 6 7 8 4 u10a el2260c + - 3 2 1 8 4 tp20 tp tp21 tp d7 mmbd301 d8 mmbd301 d6 mmbd301 d5 mmbd301 ycomp ref clock swk yadc[0:11] cm
product specification TMC2067P7C 15 preliminary information schematics (continued) -12v +12v vcc vcc vcc vcc c_clock decoupling cadc11 cadc10 cadc9 cadc8 cadc7 cadc6 cadc5 cadc4 cadc3 cadc2 cadc[0:11] cadc1 cadc0 r38 750 r41 750 c29 0.1 f c26 0.1 f r40 750 r39 47 c28 22pf c27 47pf r37 750 r35 47 c23 22pf r36 750 r34 750 c22 47pf c31 0.1 f c30 0.1 f c32 0.1 f c24 0.1 f c25 0.1 f u11 tmc1185ndc40 (msb)b1 2 b2 3 b3 4 b4 5 b5 6 b6 7 b7 8 b8 9 b9 10 (lsb)b10 11 clk 16 oe 18 msbi 19 refb 21 cm 22 reft 23 in 26 in 27 dnc 12 dnc 13 u4b el2260c + - 5 6 7 8 4 u4a el2260c + - 3 2 1 8 4 tp11 tp tp12 tp d3 mmbd301 d4 mmbd301 d2 mmbd301 d1 mmbd301 chroma ref clock e3 adc clk disable swk cadc[0:11] figure 9. c_adc
TMC2067P7C product specification 16 preliminary information schematics (continued) vcc vcc vcc vcc decoupling yadc2 yadc3 yadc4 yadc5 yadc6 yadc7 yadc8 yadc9 yadc10 yadc11 yadc1 yadc0 yadc[0:11] clock yover9 yover0 yover1 yover2 yover3 yover4 yover5 yover6 yover7 yover8 swa swb swc swd yover[0:9] swk swe swf swi swg swm swn swo sync sync swh swg swf swc swb swe swd swa e5 select e4 select u6c 74f86 9 10 8 rn1 4.7k 1 3 4 5 6 7 8 9 2 s1 sw dip-8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c46 0.1 f e6 sync disable tp16 tp tp17 tp c67 0.1 f c68 0.1 f u7 tmc2242bktc si11 34 si10 31 si9 30 si8 29 si7 28 si6 27 si5 26 si4 25 si3 24 si2 21 si1 20 si0 19 dec 39 int 38 sync 37 tco 40 rnd2 16 rnd1 17 rnd0 18 oe 41 clk 36 so15 42 so14 43 so13 44 so12 1 so11 2 so10 3 so9 4 so8 5 so7 8 s06 9 so5 10 so4 11 so3 12 so2 13 so1 14 so0 15 yadc[0:11] clock yover[0:9] sync_ck swk vcc vcc vcc decoupling c47 0.1 f c69 0.1 f c70 0.1 f vcc cadc2 cadc3 cadc4 cadc5 cadc6 cadc7 cadc8 cadc9 cadc10 cadc11 cadc1 cadc0 cadc[0:11] c_clock yover9 yover0 yover1 yover2 yover3 yover4 yover5 yover6 yover7 yover8 swa swb swc swd cover[0:9] swl swe swf swj swh swm swn swo sync sync swp swo swn swk swj swm swl swi e8 select e7 select u6d 74f86 12 13 11 rn2 4.7k 1 3 4 5 6 7 8 9 2 s1 sw dip-8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 tp18 tp tp19 tp u8 tmc2242bktc si11 34 si10 31 si9 30 si8 29 si7 28 si6 27 si5 26 si4 25 si3 24 si2 21 si1 20 si0 19 dec 39 int 38 sync 37 tco 40 rnd2 16 rnd1 17 rnd0 18 oe 41 clk 36 so15 42 so14 43 so13 44 so12 1 so11 2 so10 3 so9 4 so8 5 so7 8 s06 9 so5 10 so4 11 so3 12 so2 13 so1 14 so0 15 cadc[0:11] c_clock cover[0:9] figure 10. tmc2242
product specification TMC2067P7C 17 preliminary information schematics (continued) vcc -12v +12v -5v 96 way edge connections to the decoder board 75 ohm coax to be connected as close to the amplifier and output connector as possible. the coax is to be mounted underneath the board via holes and test points. pxck vsync hsync rgb oe vref href blank pck cref oddin ntsc/pal clamp lock d1 scl sda cref rgb hsync scl vsync sda d1 pck ntsc/pal lock oddin clamp pxck href vref reset\ oe sync_ck adclk clamp p12v xrs2 pgm_out xrs3 n12v n12v adclk xrs0 xrs1 xhsync xvsync ie anlgchr p12v ms xdir p12v blank d1_r/v0 d1_r/v1 d1_r/v2 d1_r/v3 d1_r/v4 d1_r/v5 d1_r/v6 d1_r/v7 d1_r/v8 d1_r/v9 -5v -5v -5v sync_ck cover8 cover7 cover5 d1_r/v8 cover7 yover4 cover4 d1_r/v6 cover0 cover6 d1_r/v7 d1_r/v1 d1_r/v0 cover2 cover1 yover0 cover1 cover6 yover5 d1_r/v9 yover2 yover7 yover3 yover0 yover6 d1_r/v2 cover4 cover8 cover[0:9] cover9 yover7 yover6 yover2 d1_r/v3 cover3 yover5 cover0 yover4 yover1 yover9 yover9 yover8 cover5 d1_r/v4 yover[0:9] cover3 yover1 yover8 cover2 yover3 d1_r/v5 cover9 p5v n12v pgm_out xrs2 anlgcmp p12v xrs1 adclk xvsync xrs0 anlgchr ie xhsync ms xdir xrs3 anlgcmp n12v reset sync_ck -5v -5v -5v p1c header 96 1 65 2 66 3 67 4 68 5 69 6 70 7 71 8 72 9 73 10 74 11 75 12 76 13 77 14 78 15 79 16 80 17 81 18 82 19 83 20 84 21 85 22 86 23 87 24 88 25 89 26 90 27 91 28 92 29 93 30 94 31 95 32 96 p2c euro96m 1 65 2 66 3 67 4 68 5 69 6 70 7 71 8 72 9 73 10 74 11 75 12 76 13 77 14 78 15 79 16 80 17 81 18 82 19 83 20 84 21 85 22 86 23 87 24 88 25 89 26 90 27 91 28 92 29 93 30 94 31 95 32 96 p2b euro96m 1 33 2 34 3 35 4 36 5 37 6 38 7 39 8 40 9 41 10 42 11 43 12 44 13 45 14 46 15 47 16 48 17 49 18 50 19 51 20 52 21 53 22 54 23 55 24 56 25 57 26 58 27 59 28 60 29 61 30 62 31 63 32 64 p2a euro96m 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 tp23 tp r59 75 tp22 tp jp3 termination tp25 coax mount pth7 pth 1 p1a header 96 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32 r62 10k tp24 coax mount pth8 pth 1 p1b header 96 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 r63 10k sync_ck clock clamp yover[0:9] cover[0:9] aout figure 11. op_conn
TMC2067P7C product specification 18 preliminary information schematics (continued) vdd vdda vcc +12v -12v vcc +5v -5v ground test points decoupling unused gates p5v p12v n12v n5v fb1 f bead c36 0.01uf 50v c33 22uf 35v + c35 0.1uf 50v c34 0.47uf 35v + fb2 f bead fb3 f bead c40 0.01uf 50v c37 22uf 35v + c41 22uf 35v c43 0.1uf 50v c39 0.1uf 50v c38 0.47uf 35v + c42 0.47uf 35v + + c44 0.01uf 50v u6a 74f86 1 2 3 u6b 74f86 4 5 6 c45 0.1uf pth1 pth 1 pth2 pth 1 pth3 pth 1 pth6 pth 1 pth5 pth 1 pth4 pth 1 jp2 power 6 1 2 3 4 5 6 tp14 +12v tp13 tp15 -12v cr3 orange led cr2 red led cr1 red led d10 1n4004 d11 1n4004 d9 1n4004 gnd1 gnd gnd2 gnd gnd3 gnd gnd4 gnd gnd5 gnd cr4 orange led tp27 -5v c71 22uf 35v + fb4 f bead c73 0.1uf 50v c72 0.47uf 35v + c74 0.01uf 50v d12 1n4004 figure 12. power
product specification TMC2067P7C 19 preliminary information output edge connector design notes figure 13. y/composite lpf and clamp circuit tmc2242 signal flow forward signal flow backward tmc2072 tmc3003 eprom high quality lpf low quality lpf low quality lpf low quality lpf +5v to -5v 2:1 mux high quality lpf high quality lpf fpga d.c. supply sw1 tmc22153 decoder input logic 10 bit adcs digital lpfs sw1 sw2 1 32 1 32 1 32 1 32 tmc1185 tmc1185 tmc2242 chrominance bpf and clamp circuit boards with different revision numbers may not be compatible, damage may occur if they are connected together. xpxck is a two times pixel clock fed backward. xhsync and xvsync are timing reference signals fed backward. the master/slave signal states if a board is a master or a slave board. this signal is fed forward. a master board produces the pxck, hsync, and vsync signals, and a slave board expects to receive xpxck, xhsync, xvsync, etc. xdir is fed forward and controls in which direction the xrs[3:0] data ?ws. pgm_out negative going signal pulse for initiating programming of down stream boards, generated once the devices on the board have been programmed. care must be taken to ensure that multiple devices do not try to drive the rbus at any given time. the minimum width of pgm_out is 1 m s. the reset pin on the output edge connector should be connected directly to the reset pin on the input connector. a link should be used to connect any pulse to the reset line. the master/slave, xdir, pgm_out and reset pins on the output edge connector should be connected to +5v through a 10k pull up resistor. the clamp signal is fed backward from a master to a slave board. the clamp signal should not be fed forward.
TMC2067P7C product specification 20 preliminary information output 96 way connector (male) related products tmc2068p7c decoder demonstration board tmc2069p7c triple d/a demonstration board raydemo software tmc2070p7c r-bus interface board row a row b row c 1 +5v 1 gnd 1 +5v 2 d1 or r/v [bit 0] 2 +5v 2 gnd 3 d1 or r/v [bit 1] 3 +5v 3 pxck 4 d1 or r/v [bit 2] 4 +5v 4 gnd 5 d1 or r/v [bit 3] 5 gnd 5 pck 6 d1 or r/v [bit 4] 6 analog composite/luma 6 gnd 7 d1 or r/v [bit 5] 7 gnd 7 cref 8 d1 or r/v [bit 6] 8 analog chroma 8 gnd 9 d1 or r/v [bit 7] 9 xen 9 vsync 10 d1 or r/v [bit 8] 10 gnd 10 hsync 11 d1 or r/v [bit 9] 11 xdir 11 href 12 comp, g/y, or luma [bit 0] 12 xhsync 12 vref 13 comp, g/y, or luma [bit 1] 13 xvsync 13 odd in 14 comp, g/y, or luma [bit 2] 14 xpxck 14 gnd 15 comp, g/y, or luma [bit 3] 15 xrs [bit 3] 15 ntsc/pal 16 comp, g/y, or luma [bit 4] 16 xrs [bit 2] 16 clamp pulse 17 comp, g/y, or luma [bit 5] 17 xrs [bit 1] 17 rgb 18 comp, g/y, or luma [bit 6] 18 xrs [bit 0] 18 19 comp, g/y, or luma [bit 7] 19 gnd 19 20 comp, g/y, or luma [bit 8] 20 -5v 20 21 comp, g/y, or luma [bit 9] 21 -5v 21 lock 22 chroma or b/u [bit 0] 22 -5v 22 d1 23 chroma or b/u [bit 1] 23 gnd 23 reset 24 chroma or b/u [bit 2] 24 pgm_out 24 scl 25 chroma or b/u [bit 3] 25 -12v 25 gnd 26 chroma or b/u [bit 4] 26 -12v 26 sda 27 chroma or b/u [bit 5] 27 ie (input enable) 27 oe (output enable) 28 chroma or b/u [bit 6] 28 gnd 28 blank (dac) 29 chroma or b/u [bit 7] 29 29 30 chroma or b/u [bit 8] 30 30 31 chroma or b/u [bit 9] 31 +12v 31 +12v 32 gnd 32 gnd 32 gnd
product specification TMC2067P7C 21 preliminary information notes:
TMC2067P7C product specification 22 preliminary information notes:
product specification TMC2067P7C 23 preliminary information notes:
TMC2067P7C product specification pr eliminar y infor mation 5/20/98 0.0m 001 stock# ds7002067p 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation a schematic database is a v ailable in orcad ? format, along with ep r om maps. more information on th e altera fpga is also a v ailable. contact the factor y . th e TMC2067P7C demonstration board, design documentation, and software are pr o vided as a design e xample for the cus- tomers of f airchild. f airchild makes no warranties, e xpress, statutor y , or implied r e garding merchantability or ?ness for a particular purpose. fcc compliance this board is intended for the e v aluation of f airchild semiconductor components onl y . this product has not been appr o v ed by the federal communications commission (fcc) . this product is not and may not be o f fered for sale or lease or sold or leased until the appr o v al of the fcc has been obtained. p r oduct number t emperature range speed grade screening p a c k age p a c kage marking TMC2067P7C 25 c 2 7 mhz commercial 5 b y 4 p r inted circuit board TMC2067P7C

▲Up To Search▲

Price & Availability of TMC2067P7C

	To Download TMC2067P7C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .